MIPS Acquired by AI Startup Wave Computing

MIPS Tech Inc has acquired Wave Computing, one of the myriad Silicon Valley startups designing custom-built hardware for artificial intelligence.

The company says the MIPS acquisition will add to the company’s bottom line and will be cash flow positive. MIPS will operate as an independent business unit within Wave and will continue to license IP to third parties. Financial terms of the acquisition were not disclosed.

According to Wave Computing CEO Derek Meyer, MIPS-based solutions will also be key to developing a solution for inferencing these trained neural network models in edge devices. “With working DPU commercial silicon and being in the final stages of bringing our first AI systems to market, now is the time for us to expand to the Edge of Cloud,” said Meyer. “The acquisition of MIPS allows us to combine technologies to create products that will deliver a single ‘Datacenter-to-Edge’ platform ideal for AI and deep learning. We’ve already received very strong and enthusiastic support from leading suppliers and strategic partners, as they affirm the value of data scientists being able to experiment, develop, test and deploy their neural networks on a common platform spanning to the Edge of Cloud.”

Wave Computing has developed a compute server for machine learning, which is powered by 16 of the company’s custom-built Dataflow Processing Units (DPUs). The appliance is aimed at training neural networks, the compute-intensive process that builds the deep learning models. When the system was launched in April 2017 for early access customers, Wave was saying the a single-server appliance could deliver 2.9 petaops of deep learning performance, which rose to 11.6 petaops in the four-server configuration. The product was originally scheduled for general release in Q4 of 2017, although that timeline has apparently slipped

In March 2018, the company announced it had selected a 64-bit MIPS platform as the general-purpose processor that would be integrated into Wave’s next-generation DPUs. The MIPS cores would be tasked to manage control and operating system functions on the chip. The rationale for using MIPS is that it’s a low-power architeture, well-suited to the managing system housekeeping functions on embedded hardware. The licensable design has been used extensively for this type of environment, with over 200 licensees.

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